By Tertulien Ndjountche
As digital units develop into more and more conventional in lifestyle, electronic circuits have gotten much more advanced and smaller in dimension. This e-book provides the elemental rules of electronic electronics in an available demeanour, permitting the reader to know the rules of combinational and sequential good judgment and the underlying options for the research and layout of electronic circuits. offering a hands-on process, this paintings introduces recommendations and techniques for setting up common sense equations and designing and interpreting electronic circuits. each one bankruptcy is supplemented with sensible examples and well-designed workouts with labored recommendations.
This moment of 3 volumes specializes in sequential and mathematics good judgment circuits. It covers quite a few points relating to the subsequent issues: latch and flip-flop; binary counters; shift registers; mathematics and common sense circuits; electronic built-in circuit know-how; semiconductor reminiscence; programmable common sense circuits.
Along with the 2 accompanying volumes, this e-book is an imperative software for college students at a bachelors or masters point trying to enhance their realizing of electronic electronics, and is certain sufficient to function a reference for digital, automation and laptop engineers.
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Additional info for Digital electronics 2: sequential and arithmetic logic circuits
59 shows the logic circuit and timing diagram for the positive edge-triggered JK ﬂip-ﬂop. 59. – Master-slave JK ﬂip-ﬂop. 60 shows the logic circuit and timing diagram for the master-slave JK ﬂip-ﬂop. 60. – JK ﬂip-ﬂop with asynchronous inputs. 61 shows the logic circuit and the timing diagram for the JK ﬂip-ﬂop with asynchronous inputs. – D ﬂip-ﬂop with asynchronous inputs. 62 shows the logic circuit and timing diagram for the D ﬂip-ﬂop with asynchronous inputs. – Connection of two D ﬂip-ﬂops. 63 shows logic circuit 1 and the corresponding timing diagram.
52. 53. 54. – D ﬂip-ﬂop with enable input. 24. 55. 24. – Positive edge-triggered DD ﬂip-ﬂop. 56 shows the logic circuit and the timing diagram that can be obtained from the truth table. 57 shows the logic circuit and the timing diagram for the level-triggered D ﬂip-ﬂop. 56. 57. 58 shows the logic circuit and the timing diagram that can be used to compare these two types of D ﬂip-ﬂops. 58. – Positive edge-triggered JK ﬂip-ﬂop. 59 shows the logic circuit and timing diagram for the positive edge-triggered JK ﬂip-ﬂop.
23. JK master-slave ﬂip-ﬂop: a) logic circuit; b) symbol When the master ﬂip-ﬂop is activated, its output logic state is determined not only by the inputs J and K, but also by the outputs, Q and Q, of the slave ﬂip-ﬂop. The master ﬂip-ﬂop state is then transferred to the slave ﬂip-ﬂop only when the clock signal transitions from high to low (falling edge). Thus, to ensure the normal operation of the JK master-slave ﬂip-ﬂop, the logic state taken by each input, J and K, must not change when the master ﬂip-ﬂop is activated (or the clock signal CK is set to 1).